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H5TC4G43BFR-RDA Datasheet(PDF) 29 Page - Hynix Semiconductor

No. de pieza H5TC4G43BFR-RDA
Descripción Electrónicos  4Gb DDR3L SDRAM
PDF  33 Pages
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Fabricante Electrónico  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5TC4G43BFR-RDA Datasheet(HTML) 29 Page - Hynix Semiconductor

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Rev. 1.0 / Nov. 2013
29
DDR3L-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 32.
Speed Bin
DDR3L-1333H
Unit
Note
CL - nRCD - nRP
9-9-9
Parameter
Symbol
min
max
Internal read
command to first data
tAA
13.5
(13.125)5,10
20
ns
ACT to internal read or
write delay time
tRCD
13.5
(13.125)5,10
—ns
PRE command period
tRP
13.5
(13.125)5,10
—ns
ACT to ACT or REF
command period
tRC
49.5
(49.125)5,10
—ns
ACT to PRE command
period
tRAS
36
9 * tREFI
ns
CL = 5
CWL = 5
tCK(AVG)
3.0
3.3
ns
1,2,3,4,7,11,12
CWL = 6, 7 tCK(AVG)
Reserved
ns
4
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,7
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
Reserved
ns
4
CL = 7
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1,2,3,4,7
(Optional)5,10
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 8
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1,2,3,7
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 9
CWL = 5, 6 tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1,2,3,4
CL = 10
CWL = 5, 6 tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1,2,3
(Optional)
ns
5
Supported CL Settings
5, 6, 7, 8, 9, 10
nCK
Supported CWL Settings
5, 6, 7
nCK



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