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SAFC161PI Datasheet(PDF) 91 Page - Infineon Technologies AG

No. de pieza SAFC161PI
Descripción Electrónicos  16-Bit Single-Chip Microcontroller
PDF  400 Pages
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Fabricante Electrónico  INFINEON [Infineon Technologies AG]
Página de inicio  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

SAFC161PI Datasheet(HTML) 91 Page - Infineon Technologies AG

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User’s Manual
5-9
1999-08
Interrupt Control Functions in the PSW
The Processor Status Word (PSW) is functionally divided into 2 parts: the lower byte of
the PSW basically represents the arithmetic status of the CPU, the upper byte of the
PSW controls the interrupt system of the C161PI and the arbitration mechanism for the
external bus interface.
Note: Pipeline effects have to be considered when enabling/disabling interrupt requests
via modifications of register PSW (see chapter “The Central Processing Unit”).
PSW
3URFHVVRU 6WDWXV :RUG
SFR (FF10
H/88H)
Reset value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ILVL
IEN
-
--
-
USR
0
MUL
IP
EZV
C
N
rwh
rw
-
-
-
-
rw
rwh
rwh
rwh
rwh
rwh
rwh
Bit
Function
N, C, V, Z, E,
MULIP, USR0
CPU status flags (Described in section “The Central Processing Unit”)
Define the current status of the CPU (ALU, multiplication unit).
IEN
Interrupt Enable Control Bit (globally enables/disables interrupt
requests)
0:
Interrupt requests are disabled
1:
Interrupt requests are enabled
ILVL
CPU Priority Level
Defines the current priority level for the CPU
F
H:
Highest priority level
0
H:
Lowest priority level



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