CS5504 datasheet(16/24 Pages) CIRRUS

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first rising edge of SCLK enables the shifting

mechanism. This allows the falling edges of

SCLK to shift subsequent data bits out of the

port. Note that if the MSB data bit is output and

the SCLK signal is high, the first falling edge of

SCLK will be ignored because the shifting

mechanism has not become activated. After the

first rising edge of SCLK, each subsequent fall-

ing edge will shift out the serial data. Once the

LSB is present, the falling edge of SCLK will

cause the SDATA output to go to Hi-Z and

DRDY to return high.

The serial port register

will be updated with a new data word upon the

completion of another conversion if the serial

port has been emptied, or if the CS is inactive

(high).

CS can be operated asynchronously to the

DRDY signal. The DRDY signal need not be

monitored as long as the CS signal is taken low

for at least two XIN clock cycles plus 200 ns

prior to SCLK being toggled. This ensures that

CS has gained control over the serial port.

Power Supplies and Grounding

The analog and digital supply pins to the

CS5504 are brought out on separate pins to

minimize noise coupling between the analog and

digital sections of the chip. Note that there is no

analog ground pin. No analog ground pin is re-

quired because the inputs for measurement and

for the voltage reference are differential and re-

quire no ground.

In the digital section of the

chip the supply current flows into the VD+ pin

and out of the DGND pin. As a CMOS device,

the CS5504 requires that the supply voltage on

the VA+ pin always be more positive than the

voltage on any other pin of the device. If this

requirement is not met, the device can latch-up

or be damaged. In all circumstances the VA+

voltage must remain more positive than the VD+

or DGND pins; VD+ must remain more positive

than the DGND pin.

The following power supply options are possi-

ble:

VA+ = +5V to +10V,

VA- = 0V,

VD+ = +5V

VA+ = +5V,

VA- = -5V,

VD+ = +5V

VA+ = +5V,

VA- = 0V to -5V,

VD+ = +3.3V

The CS5504 cannot be operated with a 3.3V

digital supply if VA+ is greater than +5.5V.

Figure 8 illustrates the System Connection Dia-

gram for the CS5504 using a single +5V supply.

Note that all supply pins are bypassed with

0.1

µF capacitors and that the VD+ digital sup-

ply is derived from the VA+ supply.

Figure 9 illustrates the CS5504 using dual sup-

plies of +5 and -5V.

Figure 10 illustrates the CS5504 using dual sup-

plies of +10V analog and +5V digital.

When using separate supplies for VA+ and

VD+, VA+ must be established first.

VD+

should never become more positive than VA+

under any operating condition. Remember to in-

vestigate transient power-up conditions, when

one power supply may have a faster rise time.

CS5504

DS126F1

CS5504

DS126F2

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