LCL8052ACPD datasheet(6/23 Pages) INTERSIL

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Detailed Description

Analog Section

Figure 2 shows the equivalent Circuit of the Analog Section

of both the ICL71C03/8052A and the ICL71C03/8068A in

the 3 different phases of operation. IF the RUN/HOLD pin is

left open or tied to V+, the system will perform conversions

at a rate determined by the clock frequency: 40,0002 at 41/2

digit and 4002 at 31/2 digit clock periods per cycle (see

Figure 3 for details of conversion timing).

Auto-Zero Phase I (Figure 2A)

During the Auto-Zero, the input of the buffer is connected to

VREF through switch 2, and switch 3 closes a loop around

the integrator and comparator, the purpose of which is to

charge the auto-zero capacitor until the integrator output

does not change with time. Also, switches 1 and 2 recharge

the reference capacitor to VREF.

Input Integrate Phase II (Figure 2B)

During Input Integrate the auto-zero loop is opened and the

ANALOG INPUT is connected to the BUFFER INPUT

through switch 4 and CREF. If the input signal is zero, the

buffer, integrator and comparator will see the same voltage

that existed in the previous state (Auto-Zero). Thus, the

integrator output will not change but will remain stationary

during the entire Input Integrate cycle. If VIN is not equal to

zero, and unbalanced condition exists compared to the Auto

Zero phase, and the integrator will generate a ramp whose

slope is proportional to VIN. At the end of this phase, the

sign of the ramp is latched into the polarity F/F.

Deintegrate Phase II (Figures 2C and 2D)

During the Deintegrate phase, the switch drive logic uses the

output of the polarity F/F in determining whether to close

switch 6 or 5. If the input signal is positive, switch 6 is closed

anda voltagewhich is VREF more negative than during

Auto-Zero is impressed on the BUFFER INPUT. Negative

Inputs will cause +2(VREF) to be applied to the BUFFER

INPUT via switch 5. Thus, the reference capacitor generates

the equivalent of a (+) or (-) reference from the single

reference voltage with negligible error. The reference voltage

returns the output of the integrator to the zero-crossing point

established in Phase I. The time, or number of counts,

required to do this is proportional to the input voltage. Since

the Deintegrate phase can be twice as long as the Input

Integrate Phase, the input voltage required to give a full

scale reading is 2VREF.

Differential Linearity (Difference between

Worst Case Step of Adjacent Counts and

Ideal Step)

-2V

≤ VIN ≤ +2V

0.01

Counts

Rollover Error (Difference in Reading for

Equal Positive & Negative Voltage Near

Full Scale)

-VIN ≅ +VIN ≈ 2V

0.2

0.5

Counts

Noise (Peak-To-Peak Value Not

Exceeded 95% of Time)

VIN =0V,

Full Scale = 200mV,

Full Scale = 2V

-20

-30

µV

Leakage Current at Input

VIN = 0V

530

310

Zero Reading Drift

VIN =0V,

0oCTo 70oC

-1

0.5

µV/oC

Scale Factor Temperature Coefficient

VIN =2V,

0oCTo 70oC,

Ext. Ref. 0ppm/oC

-3

-2

ppm/oC

NOTES:

10. Testedin31/2 digit (2,000 count) circuit shown in Figure 5, clock frequency 12kHz. Pin 2 71C03 connected to GND.

11. Testedin41/2 digit (20,000 count) circuit shown in Figure 5, clock frequency 120kHz. Pin 2 71C03A open.

12. Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.

13. The temperaturerange canbeextendedto70oC and beyond if the Auto-Zero and Reference capacitors are increased to absorb the high

temperature leakage of the 8068A.

System Electrical Specifications: ICL8052A/ICL71C03

V++=+15V, V+=+5V, V- = -15V,TA =25

oC, f

CLK Set for 3 Reading/Sec. (Continued)

PARAMETER

TEST

CONDITIONS

ICL8052A/ICL71C03

(NOTE 9)

ICL8052A/A/ICL71C03

(NOTE 10)

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

ICL8052A/ICL71C03, ICL8068A/ICL71C03

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