XRT7250 datasheet(85/463 Pages) EXAR

85 / 463 page

XRT7250

DS3/E3 FRAMER IC

áç

REV. 1.1.1

tween these two bit-fields and the LAPD Message

Type follows:

Bit 3 - RxCR (Command/Response) Type

This Read Only bit field indicates the value of the C/R

(Command/Response) bit-field of the latest received

LAPD Message.

Bit 2 - Rx FCS (Frame Check Sequence) Error

This Read-Only bit-field indicates whether or not the

LAPD Receiver has detected a Frame Check Se-

quence (FCS) error in the newly received LAPD Mes-

sage Frame. A "0" in this bit-field indicates that the

FCS for the latest received LAPD Message Frame is

correct. A "1" in this bit-field indicates that the FCS

for the latest received LAPD Message Frame is incor-

rect.

NOTE: For more information on the LAPD Receiver, please

see Section 3.3.3.2.

Bit 1 - End Of Message

This Read-Only bit-field indicates whether or not the

LAPD Receiver has completed its reception of the lat-

est incoming LAPD Message frame. The local µP

can poll the progress of the LAPD Receiver by peri-

odically reading this bit-field.

A "0" in this bit-field indicates that the LAPD Receiver

is still receiving the latest message from the far end

LAPD Transmitter. A "1" in this bit-field indicates that

the LAPD Receiver has finished receiving the com-

plete LAPD Message Frame.

Bit 0 - Flag Present

This Read-Only bit-field indicates whether or not the

LAPD Receiver has detected the occurrence of the

Flag Sequence byte (0x7E). A "0" in this bit-field indi-

cates that the LAPD Receiver does not detect the oc-

currence of the Flag Sequence byte. A "1" in this bit-

field indicates that the LAPD Receiver does detect

the occurrence of the Flag Sequence byte.

NOTE: For more information on the LAPD Receiver, please

see Section 3.3.3.2.

2.3.3

Receive E3 Framer Configuration Regis-

ters (ITU-T G.832)

2.3.3.1

Receive E3 Configuration & Status

Bit 7 - 5 - RxPLDType[2:0] (Received Payload

Type[2:0])

These three Read-Only bit-fields contain the Payload

Type value within the MA byte of the most recently re-

ceived E3 frame.

NOTE: The Payload Type Mismatch interrupt will be gener-

ated if the contents of these bit-fields differ from that of the

Expected Payload Types in Bits 2 through 0 within this Reg-

ister.

Bit 4 - RxFERF Algo

This Read/Write bit-field allows the user to select one

of the two RxFERF Declaration Algorithms:

Writing a "0" to this bit-field selects the following

RxFERF Declaration algorithm:

• The Receive E3 Framer declares a Far End

Receive Failure (FERF) if the FERF bit-field, within

the MA byte is set to "1" for 3 consecutive incoming

E3 Frames. Likewise, the Receive E3 Framer will

negate the Far End Receive Failure condition if the

FERF bit-field, within the MA byte is set to "0" for 3

consecutive incoming E3 Frames.

Writing a "1" to this bit-field selects the following

RxFERF Declaration algorithm:

• The Receive E3 Framer declares a Far End

Receive Failure (FERF) if the FERF bit-field, within

the MA byte is set to "1" for 5 consecutive E3

Frames. Likewise, the Receive E3 Framer will

negate the Far End Receive Failure condition if the

FERF bit-field, within the MA byte is set to "0" for 5

consecutive incoming E3 Frames.

BIT 5BIT 4MESSAGE TYPE

MESSAGE LENGTH

Test Signal Identification

76 Bytes

Idle Signal Identification

76 Bytes

CL Path Identification

76 Bytes

ITU-T Path Identification

82 Bytes

RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

RxPLDType[2:0]

RxFERF

Algo

RxTMark

Algo

RxPLDExp[2:0]

R/W

000

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