CS98200-EB datasheet(49/60 Pages) CIRRUS

49 / 60 page

DS581PP2

CS98200

Next Generation DVD Processor

8. INTERFACE DESCRIPTIONS

8.1

SDRAM Interface Pins

These pins are used to interface the CS98200 with some external SDRAM. The CS98200 can interface

with SDRAM of various sizes. Only 32-bit data width is supported. Follow the instructions in Table

15 on how to interface with any particular configuration of SDRAM.

8.2

ROM/NVRAM Interface Pins

This is the interface to the non-volatile memory that contains the firmware. See Table 16. It could be

either ROM, NVRAM – FLASH, or EEPROM, or any combination of these types of memory. This

interface can also connect to SRAM that would emulate a ROM on a development system. The bus

width is 8 bits.

Signal Name

Type

Description

11,12,13,15,16,

17,18,20,21,23,

26,27,28,29,30,

32,61, 56, 55,

53, 51, 50, 49,

48, 47, 45, 42,

40, 39, 38, 37,

36,

M_D[31:0]

Memory Data Bus. CS98200 uses all 32 bits.

90, 89, 88, 87,

85, 82, 80, 79,

78, 77, 76

M_A[10:0]

Memory Address Bus. Connect in order starting with M_A[0] to

all RAM address pins not already connected to M_BS[1:0]_N

or M_AP.

M_CKO

Memory Clock

M_CKE

Memory Clock Enable

M_BS0_N

Bank Selection. Always connect to RAM BS or BS0 pin.

M_BS1_N

Bank Selection. Always connect to RAM BS or BS0 pin.

M_AP

Memory Auto Pre-charge. Always connect to RAM AP pin.

M_RAS_N

Memory Row Address Strobe

M_CAS_N

Memory Column Address Strobe

M_WE_N

Memory Write Enable

62, 35, 33, 10

M_DQM[3:0]

IO Mask of Data Bus M_DQM[3] -> M_D[31:24]

Table 15. SDRAM Interface Pins

Signal Name

Type

Description

91,92,93,94,95,

96,99,101

NV_D[7:0]

Memory Data Bus.

90, 89, 88, 87,

85, 82, 80, 79,

78, 77, 76

M_A[10:0]

Memory Address Bus[10:0]

32, 30, 29, 28,

27, 26, 23, 21,

20, 18, 17, 16

M_D[31:16]

Memory Address Bus[23:11]

M_AP

Output Enable

M_WE_N

Write Enable.

Table 16. ROM/NVRAM Interfa c e

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