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LIS25BA Datasheet(PDF) 18 Page - STMicroelectronics |
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LIS25BA Datasheet(HTML) 18 Page - STMicroelectronics |
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18 / 32 page ![]() TDM interface specifications LIS25BA 18/32 DocID031510 Rev 4 4.5 TDM configurations In the following subsections all the LIS25BA TDM configurations programmable through the I²C interface will be detailed. 4.5.1 Configuration 1 No delay: SLOT0 data MSB is sampled on the first rising edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to zero) Data valid: data valid on the rising edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal to zero) Figure 9. WCLK, SDOUT change on the falling edge of BCLK and are valid on the rising edge of BCLK, no delay Note: Setup and hold times are defined in Table 6: TDM interface characteristics. 4.5.2 Configuration 2 No delay: SLOT0 data MSB is sampled on the first falling edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to zero) Data valid: data valid on the falling edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal to one) Figure 10. WCLK, SDOUT change on the rising edge of BCLK and are valid on the falling edge of BCLK, no delay Note: Setup and hold times are defined in Table 6: TDM interface characteristics. |
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