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IS25LP032D-RHLA3:P Datasheet(PDF) 53 Page - Integrated Silicon Solution, Inc

No. de pieza IS25LP032D-RHLA3:P
Descripción Electrónicos  SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  118 Pages
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Fabricante Electrónico  ISSI [Integrated Silicon Solution, Inc]
Página de inicio  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP032D-RHLA3:P Datasheet(HTML) 53 Page - Integrated Silicon Solution, Inc

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IS25LP032D
IS25WP032D
Integrated Silicon Solution, Inc.- www.issi.com
53
Rev. A12
08/04/2020
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)
A Block Erase (BER) instruction erases a 32/64Kbyte block. Before the execution of a BER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the
completion of a block erase operation.
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after the
CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic automatically
handles the erase voltage and timing.
Figure 8.16 Block Erase (64K) Sequence In SPI Mode
Instruction = D8h
23
CE #
SCK
SI
3
2
SO
1
0
3-byte Address
High Impedance
22
21
...
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
Mode 3
Mode 0
Figure 8.17 Block Erase (64K) Sequence In QPI Mode
D8h
CE#
SCK
IO[3:0]
3-byte Address
0
1
2
3
4
5
6
7
Mode 3
Mode 0
23:20 19:16 15:12 11:8
7:4
3:0



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