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IS25LP064A-RGLA3 Datasheet(PDF) 76 Page - Integrated Silicon Solution, Inc

No. de pieza IS25LP064A-RGLA3
Descripción Electrónicos  3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  99 Pages
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Fabricante Electrónico  ISSI [Integrated Silicon Solution, Inc]
Página de inicio  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP064A-RGLA3 Datasheet(HTML) 76 Page - Integrated Silicon Solution, Inc

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IS25LP064A/032A
Integrated Silicon Solution, Inc.- www.issi.com
76
Rev. A
11/06/2015
Figure 8.59 FRQDTR Sequence (with command decode cycles)
CE #
SCK
Instruction = EDh
CE #
SCK
3-byte Address
High Impedance
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
21
22
23
24
25
26
...
Mode 3
Mode 0
tV
20 16 12
5 1
21 17 13
Data
Out
4 0
IO0
IO1
IO0
22 18 14
23 19 15
8 4
0
9 5
1
10 6
2
11 7
3
3 Dummy Cycles
IO2
IO3
IO1
IO2
IO3
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
13
5 1
4 0
6 2
7 3
Mode Bits
...
...
...
...
5 1
4 0
6 2
7 3
Data
Out
Notes:
1. If the mode bits=AXh (
where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.



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