ADGM1004JCPZ-R2 datasheet(7/32 Pages) AD

No. de pieza	ADGM1004JCPZ-R2

Descripción Electrónicos	0 Hz/DC to 13 GHz, 2.5 kV HBM ESD, SP4T, MEMS Switch with Integrated Driver

PDF	32 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

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7 / 32 page

Data Sheet

ADGM1004

Rev. D | Page 7 of 32

TIMING CHARACTERISTICS

VDD = 3.0 V to 3.6 V, GND = 0 V, and all specifications TMIN to TMAX = 0°C to +85°C, unless otherwise noted.

Table 2.

Parameter

Description

Limit at TMIN

Limit at TMAX

Unit

SCLK period

100

SCLK high pulse width

SCLK low pulse width

CS falling edge to SCLK active edge

Data setup time

Data hold time

SCLK active edge to CS rising edge

CS falling edge to SDO data available

t91

SCLK falling edge to SDO data available

t10

CS rising edge to SDO returns to high impedance

t11

CS high time between SPI commands

100

t12

SCLK edge rejection to CS falling edge

t13

CS rising edge to SCLK edge rejection

1 Measured with a 20 pF load, t9 determines the maximum SCLK frequency when the SDO pin is used.

ADGM1004JCPZ-R2 Datasheet(PDF) 7 Page - Analog Devices