CS4210 datasheet(69/102 Pages) NSC

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4.4.15 IRMultiChanMask Registers

An isochronous channel mask is used to enable packet

receives from up to 64 specified isochronous data chan-

nels. Software enables receives for any number of isochro-

nous channels by writing ones to the corresponding bits in

the:

BAR0+Offset 70h: IRMultiChanMaskHi Set

BAR0+Offset 78h: IRMultiChanMaskLo Set

To disable receives for any isochronous channels, software

writes ones to the corresponding bits in the:

BAR0+Offset 74h: IRMultiChanMaskHi Clear

BAR0+Offset 7Ch: IRMultiChanMaskLo Clear

A read of each IRMultiChanMask register shows which

channels are enabled; a one for enabled, a zero for dis-

abled. The IRMultiChanMask registers are not changed by

a bus reset. The state of these registers is undefined fol-

lowing a hard reset or soft reset.

Table 4-25. IRMultChanMask Registers

Bit

Name

Access

Reset

Description

BAR0+Offset 70h

IRMultiChanMaskHi Set Register

31:0

IsochChannel[63:32]

RSC

Undef

Isochronous Channels [63:32]: Bits [31:0] correspond to channels

[63:32]. Set to one to enable receives to the corresponding channel.

BAR0+Offset 74h

IRMultiChanMaskHi Clear Register

31:0

IsochChannel[63:32]

RSC

Undef

Isochronous Channels [63:32]: Bits [31:0] correspond to channels

[63:32]. Set to one to disable receives to the corresponding channel.

BAR0+Offset 78h

IRMultiChanMaskLo Set Register

31:0

IsochChannel[31:0]

RSC

Undef

Isochronous Channels [31:0]: Bits [31:0] correspond to channels [31:0].

Set to one to enable receives to the corresponding channel.

BAR0+Offset 7Ch

IRMultiChanMaskLo Clear Register

31:0

IsochChannel[31:0]

RSC

Undef

Isochronous Channels [31:0]: Bits [31:0] correspond to channels [31:0].

Set to one to disable receives to the corresponding channel.

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