STM32MP157F datasheet(34/260 Pages) STMICROELECTRONICS

34 / 260 page

Functional overview

STM32MP157C/F

34/260

DS12505 Rev 5

3.10.2

System reset sources

The power-on reset initializes all registers while the system reset reinitializes the system

except for the debug, part of the RCC and power controller status registers, as well as the

backup power domain.

An application reset is generated from one of the following sources:

–

a reset from NRST pad

–

a reset from POR and PDR signal (generally called power-on reset)

–

a reset from BOR (generally called brownout)

–

a reset from the independent watchdogs 1

–

a reset from the independent watchdogs 2

–

a software reset from the Cortex-M4 (MCU)

–

a software reset from the Cortex-A7 (MPU)

–

a failure on HSE, when the clock security system feature is activated

A system reset is generated from one of the following sources:

–

An application reset,

–

A reset from POR_VDDCORE signal,

–

Every time the system exits from Standby.

3.11

Hardware semaphore (HSEM)

The HW semaphore block provides 64 (32-bit) register-based semaphores.

The semaphores can be used to ensure synchronization between different processes

running on a core and between different cores. The HSEM provides a non blocking

mechanism to lock semaphores in an atomic way. The following functions are provided:

•

Locking a semaphore can be done in 2 ways:

–

2-step lock: by writing CoreID and ProcessID to the semaphore, followed by a

read check.

–

1-step lock: by reading the CoreID from the semaphore.

•

Interrupt generation when a semaphore is freed.

–

Each semaphore may generated an interrupt on one of the interrupt lines.

•

Semaphore clear protection.

–

A semaphore is only cleared when CoreID and ProcessID matches.

•

Global semaphore clear per CoreID.

3.12

Inter-processor communication controller (IPCC)

The inter-processor communication controller (IPCC) is used for communicating data

between two processors.

The IPCC block provides a non blocking signaling mechanism to post and retrieve

communication data in an atomic way. It provides the signaling for four channels:

•

two channels in the direction from processor 1 to processor 2

•

two channels in the opposite direction.

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