VIPER318HDTR datasheet(18/40 Pages) STMICROELECTRONICS

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This kind of operation, together with the extremely low IC quiescent current, allows very low input power

consumption in no-load and light load, while the low DRAIN peak current value, IDLIM_PFM, prevents any

audible noise which could arise from low switching frequency values. When the output load is increased, VCOMP

increases and PFM is exited. VCOMP reaches its maximum at VCOMPH, corresponding to the DRAIN current

limitation (IDLIM).

4.11

Overload protection

In order to manage the overload condition the IC embeds the following main blocks: the OCP comparator to turn

off the power MOSFET when the drain current reaches its limit (IDLIM), the up and down OCP counter to define

the turn-off delay time in case of continuous overload (tOVL = 50 ms typ.) and the timer to define the restart time

after protection tripping (tRESTART = 1 sec, typ.).

In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than

the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn off of the

power switch is triggered by the OCP comparator instead of by the PWM comparator. Every cycle this condition is

met, the OCP counter is incremented. If the fault condition persists for a time greater than tOVL (corresponding to

the counter end-of-count), the protection is tripped, the PWM is disabled for tRESTART, then it resumes switching

with soft-start and, if the fault is still present, it is disabled again after tOVL. The OLP management prevents the IC

from being indefinitely operated at IDLIM and the low repetition rate of the restart attempts of the converter avoids

overheating the IC in case of repeated fault events.

After the fault removal, the IC resumes working normally. If the fault is removed before the protection tripping

(before tOVL), the tOVL counter is decremented on a cycle-by-cycle basis down to zero and the protection is not

tripped. If the fault is removed during tRESTART, the IC waits for the tRESTART period ot have elapsed before

resuming switching.

In fault condition, VCC is kept between VCSon and VCCon by the periodical activation of the HV current source,

which recharges the VCC capacitor to VCcon any time the IC internal consumption discharges it to VCson.

Figure 28. Overload protection

time

VCC

VCCon

VCSon

IDRAIN

IDLIM

tOVL

tRESTART

tSS

tOVL

Overload applied

tSS

time

Overload removed

tRESTART

4.12

Undervoltage protection

If the voltage across the UVP pin (VUVP) falls below the internal threshold VUVP_th (0.4 V typ.) for a time greater

than tUVP_DEB (30 ms, typ.), the IC is disabled and its consumption is reduced to ultra-low values (Iq_DIS).

When VUVP rises above VUVP_th, the IC must wait tUVP_REST (30 ms, typ.) before resuming switching.

Both tUVP_DEB and tUVP_REST are intended to filter out possible noises/disturbances of the line, which could affect

the correct operation of the function. They are obtained through two separate up/down counters:

DEB (REST) up/down counter has a deb_eoc (rest_eoc) end-of-count. The operation is illustrated in

Figure 29. UVP timing.

If the counter starts from zero and counts always up, end-of-count is reached in a time interval tUVP_DEB

(tUVP_REST).

VIPER31

Overload protection

DS13285 - Rev 3

page 18/40

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