AD9546SLASHPCBZ datasheet(203/205 Pages) AD

203 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 203 of 205

In read mode, the master device (receiver) receives the last data

byte from the slave device (transmitter) but does not pull SDA

low during the ninth clock pulse (a nonacknowledge bit). By

receiving the nonacknowledge bit, the slave device knows that

the data transfer is finished and enters idle mode.

The master device then takes the data line low during the low

period before the 10th clock pulse, and high during the 10th

clock pulse to assert a stop condition.

A start condition can be used instead of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

Data Transfer Format

The write byte format is used to write a register address to the

RAM starting from the specified RAM address (see Table 116).

The send byte format is used to set up the register address for

subsequent reads (see Table 117). The receive byte format is

used to read the data byte(s) from RAM starting from the

current address (see Table 118). The read byte format is the

combined format of the send byte and the receive byte (see

Table 119).

SDA

START CONDITION

STOP CONDITION

SCL

Figure 142. Start and Stop Conditions

3 TO 7

SDA

SCL

MSB

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

Figure 143. Acknowledge Bit

3 TO 7

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

SDA

SCL

MSB

Figure 144. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

3 TO 7

ACK FROM

MASTER RECEIVER

NONACK FROM

MASTER RECEIVER

SDA

SCL

Figure 145. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge from Slave

AD9546/PCBZ Datasheet(PDF) 203 Page - Analog Devices

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