AD9546SLASHPCBZ datasheet(199/205 Pages) AD

199 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 199 of 205

SERIAL CONTROL PORT

SERIAL CONTROL PORT OVERVIEW

The AD9546 serial control port is a flexible, synchronous serial

communications port that provides a convenient interface to

many industry-standard microcontrollers and microprocessors.

The AD9546 serial control port is compatible with most

synchronous transfer formats, including I²C, Motorola SPI, and

Intel SSR protocols. The serial control port allows read/write

access to the AD9546 register map.

The AD9546 uses the Analog Devices unified SPI protocol (see

the Analog Devices Serial Control Interface Standard). The

unified SPI protocol guarantees that all new Analog Devices

products using the unified protocol have consistent serial port

characteristics. The SPI port configuration is programmable via

Unified SPI differs from the SPI port found on older Analog

Devices products, such as the AD9557 and AD9558, in the

following ways:

•

Unified SPI does not have byte counts. A transfer is

terminated when the CSB signal goes high. The W1 and

W0 bits in the traditional SPI become the A12 and A13

bits of the register address (see Table 113). This format is

much like streaming mode in the traditional SPI.

•

The address ascension bit (Register 0x0000) controls

whether register addresses are automatically incremented

or decremented regardless of the LSB/MSB first setting. In

a traditional SPI, LSB first mode dictated auto-incrementing

and MSB first mode dictated auto-decrementing of the

•

The first 16 register addresses of devices that adhere to the

unified serial port have a consistent structure.

SPI/I²C PORT SELECTION

Although the AD9546 supports both the SPI and I2C serial port

protocols, only one is active following power-up (as determined

by the M4 pin during the start-up sequence). The only way to

change the serial port protocol is to reset (or power cycle) the

device. See Table 103 for the I2C address assignments.

SPI SERIAL PORT OPERATION

Pin Descriptions

The serial clock (SCLK) signal serves as the serial shift clock.

This pin is an input. SCLK synchronizes serial control port read

and write operations. The rising edge SCLK registers write data

bits, and the falling edge registers read data bits. The SCLK line

supports a maximum clock rate of 50 MHz.

The user can configure the SPI port hardware configuration

and data format via the Register 0x0000. The hardware

configurations are 3-wire bidirectional (default) or 4-wire

unidirectional mode and the data formats are MSB first

(default) or LSB first. The 3-wire mode uses the serial data

input/output (SDIO) signal for transferring data in both

directions. The 4-wire mode uses SDIO for transferring data to

the AD9546, and SDO for transferring data from the AD9546.

The output drive strength of the SDO and SDIO pins is

selectable via Bit 7 of Register 0x0109.

The chip select (CSB) signal is an active low control that gates

read and write operations. Assertion (active low) of CSB

initiates a write or read operation to the AD9546 SPI port. The

user can transfer any number of data bytes in a continuous stream.

The register address is automatically incremented or decremented

based on the setting of the address ascension bit (Register 0x0000).

The user must deassert CSB following the last byte transferred,

thereby ending the stream mode. CSB is internally connected to

a 10 kΩ pull-up resistor. When CSB is high, SDIO and SDO

enter a high impedance state.

Implementation Specific Details

The Analog Devices Serial Control Interface Standard provides

a detailed description of the unified SPI protocol and covers

items such as timing, command format, and addressing. The

unified SPI protocol defines the following device specific items:

•

Analog Devices unified SPI protocol revision: 1.0

•

Chip type: 0x5

•

Product ID: 0x0121

•

Physical layer: 3-wire and 4-wire supported and 1.5 V,

1.8 V, and 2.5 V operation supported

•

Optional single-byte instruction mode: not supported

•

Data link: not used

•

Control: not used

Communication Cycle—Instruction Plus Data

The unified SPI protocol consists of a two-part communication

cycle. The first part is a 16-bit instruction word coincident with

the first 16 SCLK rising edges. The second part is the payload,

the bits of which are coincident with SCLK rising edges. The

instruction word provides the AD9546 serial control port with

information regarding the payload. The instruction word

includes the R/W bit that indicates the direction of the payload

transfer (that is, a read or write operation). The instruction

word also indicates the starting register address of the first

payload byte.

IO Update

In general, there are two sets of serial port registers: buffer

registers and active registers. When the SPI port receives data, it

deserializes the data, which collects in the buffer registers. In

most cases, the output of the buffer registers route to the input

of the active registers rather than directly to the intended circuit

blocks within the device. As such, when the user writes SPI

data, the intended functional blocks within the device are

unaffected by the newly written data.

AD9546/PCBZ Datasheet(PDF) 199 Page - Analog Devices

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