18

Am79C02/03/031(A) Data Sheet

Master Clock

For 2.048 MHz ±100 ppm or 4.096 MHz ±100 ppm operation:

Notes:

1. DCLK may be stopped in the High or Low state indefinitely without loss of information. If CS makes a transition to the Low

state, the last byte received is interpreted by the Microprocessor Interface logic.

2. The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency and synchronous to the MCLK

frequency. The actual PCLK rate is dependent on the number of channels allocated within a frame. The DSLAC supports 2–

128 channels. A PCLK of 1.544 MHz can be used for standard US transmission systems. The minimum clock frequency is

128 kHz.

3. TSC is delayed from FS by a typical value of N

4. There is a special conflict detection circuitry that prevents high-power dissipation from occurring when the DXA or DXB pins

of two DSLAC devices are tied together and one DSLAC device starts to transmit before the other has gone into a high-

impedance state.

5. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.

7. The DSLAC device requires 40 cycles of the 8 MHz internal clock (5 µs) between SIO operations. If the MPI is being accessed

while the MCLK input is not active, a Chip Select Off time of 20 µs is required.

SWITCHING WAVEFORMS

Input and Output Waveforms for AC Tests

Master Clock Timing

No.

Symbol

Parameter

Min

Typ

Max

Units

35

Master Clock Period (2.048 MHz)

488.23

488.28

488.33

ns

Master Clock Period (4.096 MHz)

244.11

244.14

244.17

36

Rise Time of Clock

15

37

Fall Time of Clock

15

38

MCLK High Pulse Width (2.048 MHz)

200

MCLK High Pulse Width (4.096 MHz)

80

39

MCLK Low Pulse Width (2.048 MHz)

200

MCLK Low Pulse Width (4.096 MHz)

80

Test

Points

2.0

0.8

2.0

0.8

2.4

0.45

09875H-012

09875H-013

35

36

39

38

37