HT48CA6 datasheet(4/31 Pages) HOLTEK

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A.C. Characteristics

Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VDD

Conditions

fSYS

System Clock

400

4000

kHz

tRES

External Reset Low Pulse Width

¾¾

tSST

System Start-up timer Period

Power-up or wake-up

from HALT

1024

tSYS

Note: tSYS=1/fSYS

HT48CA6

Rev. 1.10

July 26, 2002

Functional Description

Execution flow

The HT48CA6 system clock can be derived from a crys-

tal/ceramic resonator oscillator. It is internally divided

into four non-overlapping clocks. One instruction cycle

consists of four system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to effectively execute within 1 cycle. If an instruction

changes the program counter, two cycles are required to

complete the instruction.

Program counter

- PC

The 10-bit program counter (PC) controls the sequence

in which the instructions stored in program ROM are ex-

ecuted and its contents specify a maximum of 1024 ad-

dresses.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by 1. The program counter then points to

the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set or return from subroutine, the PC manipulates the

program transfer by loading the address corresponding

to each instruction.

The conditional skip is activated by instruction. Once the

condition is met, the next instruction, fetched during the

current instruction execution, is discarded and a dummy

cycle replaces it to get the proper instruction. Otherwise

proceed with the next instruction.

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

. e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

. e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

. e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

S y s t e m C l o c k

I n s t r u c t i o n C y c l e

P C

Execution flow

Mode

Program Counter

Initial reset

000000000

Skip

PC+2

Loading PCL

Jump, call branch

Return from subroutine

Program counter

Note: *9~*0: Program counter bits

S9~S0: Stack register bits

#9~#0: Instruction code bits

@7~@0: PCL bits

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