MCP6V37-ESLASHMS datasheet(6/50 Pages) MICROCHIP

6 / 50 page

MCP6V36/6U/7/9

DS20006209A-page 6

 2019 Microchip Technology Inc.

1.3

Timing Diagrams

FIGURE 1-1:

Amplifier Start Up.

FIGURE 1-2:

Offset Correction Settling

Time.

FIGURE 1-3:

Output Overdrive Recovery.

1.4

Test Circuits

The circuits used for most DC and AC tests are shown

in Figure 1-4 and Figure 1-5. Lay the bypass capacitors

out

discussed

Section 4.3.10

“Supply

Bypassing and Filtering”. RN is equal to the parallel

combination of RF and RG to minimize bias current

effects.

FIGURE 1-4:

AC and DC Test Circuit for

Most Noninverting Gain Conditions.

FIGURE 1-5:

AC and DC Test Circuit for

Most Inverting Gain Conditions.

The circuit in Figure 1-6 tests the input’s dynamic

behavior (i.e., IMD, tSTR, tSTL and tODR). The

potentiometer balances the resistor network (VOUT

should equal VREF at DC). The op amp’s Common-

mode input voltage is VCM =VIN/2. The error at the

input (VERR) appears at VOUT with a noise gain of

10 V/V.

FIGURE 1-6:

Test Circuit for Dynamic

Input Behavior.

VDD

VOUT

1.001(VDD/3)

0.999(VDD/3)

tSTR

1.8V to 5.5V

1.8V

VIN

VOS

VOS +100 µV

VOS –100 µV

tSTL

VIN

VOUT

VDD

VSS

tODR

VDD/2

VDD

VOUT

VIN

VDD/3

1µF

100 nF

RISO

MCP6V3X

VDD

VOUT

VDD/3

VIN

1µF

100 nF

RISO

MCP6V3X

VDD

VOUT

1µF

RISO

11.0 kΩ

249 Ω

11.0 kΩ

500 Ω

VIN

VREF =VDD/3

0.1%

25 turn

100 kΩ

0.1%

0 Ω

20 pF

open

100 nF

MCP6V3X

MCP6V37-E/MS Datasheet(PDF) 6 Page - Microchip Technology

MCP6V37-E/MS Datasheet(HTML) 6 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Descarga

Enlace URL