STW8009 datasheet(25/55 Pages) STMICROELECTRONICS

25 / 55 page

STw8009/STw8019

Control registers

25/55

selrst_inc: Choice of Digital Frequency Synthesizer increment after soft reset or when

ph_rst_mode = ‘01’ . See Register 8.

(*) 0 = hard wired value (depending on TV standard)

1 = soft (value from registers 10 to 12)

bkdacN: blanking of DACs (N = 1 or 2)

(*) 0 = DAC N in normal operation

1 = DAC N input code forced to black level for C output or blanking level for Y or CVBS

output depending of dac12_conf bit of configuration13 register.

dacinv: ‘Inverts’ DAC codes to compensate for an inverting output stage in the application

(*) 0 = non inverted DAC inputs (outputs)

1 = inverted DAC inputs (outputs)

softreset: software reset

(*) 0 = no reset

1 = software reset

Note:

Bit ‘softreset’ is automatically reset after internal reset generation. Software reset is active

during 4 PIX_CLK periods. When softreset is activated, all the device is reset as with

hardware reset except for the first nine user registers (registers 0 to 8:

configurations).Registers 10 up to 14 (increment and phase of oscillator), 25-30, 31-33 and

39-42 are never reset (hard/soft).

configuration5

Address: 0x0005

Type: R/W

content

selrst_

inc

bkdac1

bkdac2

dacinv

default

[0]

configuration6

Address: 0x0006

Type: R/W

content

softreset

jump

dec_ninc

free_

jump

cfc1

cfc0

maxdyn

default

0100

[0]

Table 9.

jump, dec_ninc, free_jump

jump

dec_nin

free_ju

update mode

Normal mode (no line skip/insert capability)

ITU-R (CCIR): 313/312 or 263/262

non-interlaced: 312/312 or 262/262

(*)

Manual mode for line insert (“dec_ninc”=0) or skip

(“dec_ninc”=1) capability.

Both fields of all the frames following the writing of this value

are modified according to “lref” and “ltar” bits of registers 21-

22-23 (by default, “lref”=0 and “ltar”=1 which leads to normal

mode above).

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