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FXLS8967AF Datasheet(PDF) 40 Page - NXP Semiconductors |
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FXLS8967AF Datasheet(HTML) 40 Page - NXP Semiconductors |
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40 / 98 page  NXP Semiconductors FXLS8967AF 3-Axis Low-g Accelerometer Bit 7 6 5 4 3 2 1 0 Name BUF_Y[7:0] Reset — — — — — — — — Access R R R R R R R R Table 37. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_CONFIG2[LE_BE] = 0 bit allocation Bit 7 6 5 4 3 2 1 0 Name SX SX SX SX BUF_Y[11:8] Reset — — — — — — — — Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Name BUF_Z[7:0] Reset — — — — — — — — Access R R R R R R R R Table 38. BUF_Z_LSB and BUF_Z_MSB registers (addresses 10h, 11h) with SENS_CONFIG2[LE_BE] = 0 bit allocation Bit 7 6 5 4 3 2 1 0 Name SX SX SX SX BUF_Z[11:8] Reset — — — — — — — — Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Name BUF_X[11:4] Reset — — — — — — — — Access R R R R R R R R Table 39. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_CONFIG2[LE_BE] = 1 bit allocation Bit 7 6 5 4 3 2 1 0 Name BUF_X[3:0] 0 0 0 0 Reset — — — — — — — — Access R R R R R R R R FXLS8967AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Objective data sheet Rev. 1 — 27 April 2021 40 / 98 |
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