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PCF8553DTT/A Datasheet(PDF) 10 Page - NXP Semiconductors |
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PCF8553DTT/A Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 51 page  NXP Semiconductors PCF8553 40 × 4 LCD segment driver • The address pointer is cleared (set to logic 0) • The display and the internal oscillator are disabled • The display registers are set to logic 0 Remark: The hardware reset overrides the POR see Section 7.3.2. 7.3.4 Command: Software_reset The internal registers including the display registers and the address pointer (set to logic 0) of the device are reset by the Software_reset command. Bit Symbol Value Description software reset 0000 0000[1] no reset 7 to 0 SR[7:0] 0010 1100 software reset Table 8. Software_reset - software reset command register (address 00h) bit description [1] Default value. 7.4 Display data register mapping The example in Table 9 and Figure 5 illustrates the segment and backplane mapping of the display in relation to the display RAM. For example, in 1:4 multiplex drive mode, the backplanes are served by signals COM0 to COM3 and the segments are driven by signals SEG0 to SEG39. Contents of addresses 04h to 08h are allocated to the first row (COM0) starting with the LSB driving the leftmost element and moving forward to the right with increasing bit position. If a bit is logic 0, the element is off, if it is logic 1 the element is turned on. All register content is LSB to MSB left to right. Addresses 09h to 0Dh serve COM1 signals, addresses 0Eh to 12h serve COM2 signals, and addresses 13h to 17h serve COM3 signals. For displays with fewer segments/elements the unused bits are ignored. Segments SEG0 to SEG7 SEG8 to SEG15 SEG16 to SEG23 SEG24 to SEG31 SEG32 to SEG39 Backplanes[1] LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB 1:4 multiplex drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h COM1 content of 09h content of 0Ah content of 0Bh content of 0Ch content of 0Dh COM2 content of 0Eh content of 0Fh content of 10h content of 11h content of 12h COM3 content of 13h content of 14h content of 15h content of 16h content of 17h 1:3 multiplex drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h COM1 content of 09h content of 0Ah content of 0Bh content of 0Ch content of 0Dh COM2 content of 0Eh content of 0Fh content of 10h content of 11h content of 12h 1:2 multiplex drive mode Table 9. Register to segment and backplane mapping PCF8553 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 20 April 2021 10 / 51 |
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