PLL702-02

Low EMI Peripheral Clock Generator for Notebook & Motherboards

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 08/30/05 Page 4

Connecting a bi-directional pin

The PLL702-02 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs

have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can

be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in

order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-

up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin

and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-

directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up

resistor.

Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor

may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.

For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the

internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the

pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is

recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application

Diagram).

Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is

in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be

dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is particularly

true when driving 74FXX TTL components.

APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP

Latch

Power Up

Reset

Jumper options

R

Clock Load

Latched

Input

Output

EN

VDD

R

up

Bi-directional pin

R

RB

NOTE: Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.

Internal to chip

External Circuitry