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DA7400 Datasheet(PDF) 4 Page - Dialog Semiconductor

No. de pieza DA7400
Descripción Electrónicos  High Performance Stereo Codec Final
PDF  135 Pages
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Fabricante Electrónico  DIALOG [Dialog Semiconductor]
Página de inicio  http://www.dialog-semiconductor.com/
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DA7400 Datasheet(HTML) 4 Page - Dialog Semiconductor

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DA7400
High Performance Stereo Codec
Final
Datasheet
Revision 3.0
03-Jul-2020
CFR0011-120-00
4 of 135
© 2020 Dialog Semiconductor
11.6 Digital to Analog Converter ................................................................................................. 46
11.7 Headphone Amplifiers......................................................................................................... 46
11.8 Headphone Charge Pump .................................................................................................. 46
12 Digital Audio Interface ................................................................................................................ 47
12.1 Introduction ......................................................................................................................... 47
12.2 Features .............................................................................................................................. 47
12.3 Block Diagram ..................................................................................................................... 47
12.3.1
Block Architecture................................................................................................ 47
12.3.1.1
Sample Rate Converter ................................................................... 47
12.4 DAI Functional Description ................................................................................................. 48
12.4.1
Master or Slave Mode.......................................................................................... 48
12.4.2
DAI Channels....................................................................................................... 49
12.4.2.1
I2S Format........................................................................................ 49
12.4.2.2
DSP Format ..................................................................................... 49
12.4.2.3
Left Justified Format ........................................................................ 49
12.4.2.4
Right Justified Format...................................................................... 50
12.4.3
Time Division Multiplexing Mode ......................................................................... 50
12.5 Sample Rate Converter....................................................................................................... 52
13 Digital Microphones Interface .................................................................................................... 53
13.1 Introduction ......................................................................................................................... 53
13.2 Features .............................................................................................................................. 53
13.3 Block Diagram ..................................................................................................................... 53
13.4 Block Architecture ............................................................................................................... 53
13.5 Physical Interface................................................................................................................ 53
13.5.1
Sampling DMIC Data ........................................................................................... 53
13.6 DMIC Router ....................................................................................................................... 54
14 Signal Generator ......................................................................................................................... 55
14.1 Introduction ......................................................................................................................... 55
14.2 Block Diagram ..................................................................................................................... 55
14.3 Block Architecture ............................................................................................................... 55
14.3.1
Tone Generator ................................................................................................... 55
14.3.2
Noise Generator .................................................................................................. 55
15 Programming ............................................................................................................................... 56
15.1 Overview ............................................................................................................................. 56
15.1.1
Set Switching ....................................................................................................... 56
15.1.1.1
Set Switch Operation ....................................................................... 56
15.1.2
Programming Model ............................................................................................ 57
15.1.2.1
Programming Model 1: SET0 for STANDBY and SET1 for
ACTIVE ............................................................................................ 57
15.1.2.2
Programming Model 2: Flexible ....................................................... 57
15.1.3
Default Values ..................................................................................................... 57
15.2 Sequencer ........................................................................................................................... 57
15.2.1
Set Programming................................................................................................. 58
15.2.1.1
Path Setup ....................................................................................... 58
15.2.2
Shared Sequencer Registers .............................................................................. 58
15.2.3
Sequencer Status Monitoring .............................................................................. 59
15.3 Clocking .............................................................................................................................. 59



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