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ADMV8416ACPZ-R5 Datasheet(PDF) 6 Page - Analog Devices

No. de pieza ADMV8416ACPZ-R5
Descripción Electrónicos  6.3 GHz to 18 GHz, Tunable Band-Pass Filter
PDF  16 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADMV8416ACPZ-R5 Datasheet(HTML) 6 Page - Analog Devices

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ADMV8416
Data Sheet
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
NC
2
NC
3
NC
4
GND
5
RFIN
6
GND
7
NC
8
NC
9
NC
10
NC
23 NC
24 NC
25 GND
26 RFOUT
27 GND
28 NC
29 NC
30 NC
22 NC
21 NC
ADMV8416
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT. THESE PINS ARE NOT CONNECTED
INTERNALLY. ALL DATA SHOWN WITHIN WAS MEASURED
WITH THESE PINS CONNECTED TO RF AND DC GROUND
EXTERNALLY.
2. CONNECT THE EPAD TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 3, 7 to 10, 14, 17, 20,
21 to 24, 28 to 40
NC
No Connect. These pins are not connected internally. All data shown within was measured with
these pins connected to RF and dc ground externally.
4, 6, 12, 16, 18, 25, 27
GND
Ground. Connect these pins to RF and dc ground.
5
RFIN
RF Input. This pin is dc-coupled and matched to 50 Ω. Blocking capacitors are required if the RF
line potential is not equal to 0 V.
11
VEE
Negative Supply Voltage. VEE is −5 V.
13
VDD
Positive Supply Voltage. VDD is 5 V.
15
VCTL
Control Voltage for Band Selection. The band-pass filter is in the high band when VCTL = 0 V and in
the low band when VCTL = 2.5 V.
19
VTUNE
Center Frequency Control Voltage of the Band-Pass Filter. The voltage can vary from 0 V to 15 V.
26
RFOUT
RF Output. This pin is dc-coupled and matched to 50 Ω. Blocking capacitors are required if the
RF line potential is not equal to 0 V.
EPAD
Exposed Pad. Connect the EPAD to RF and dc ground.
INTERFACE SCHEMATICS
VDD
VCTL
Figure 3. VCTL and VDD Interface Schematic
125Ω
15pF
VTUNE
59pF
3.3Ω
0.5nH
Figure 4. VTUNE Interface Schematic
VEE
Figure 5. VEE Interface Schematic
GND
Figure 6. GND Interface Schematic
RFIN/
RFOUT
Figure 7. RFIN and RFOUT Interface Schematic



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