ICS16859 datasheet(6/8 Pages) ICST

6 / 8 page

ICSSSTV16859

0003G—05/21/02

Notes:

1. CL incluces probe and jig capacitance.

2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA.

3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,

Zo=50W, input slew rate = 1 V/ns ±20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per measurement.

5. VTT = VREF = VDDQ/2

6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input.

7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.

8. tPLH and tPHL are the same as tpd

Test Point

Load Circuit

From Output

Under Test

C= 30 pF

(see Note 1)

VTT

R =

L 50W

LVCMOS

RESET#

Input

LVCMOS

RESET#

Input

DDQ

tinact

tact

(see note 2)

IDDH

IDDL

10%

90%

Voltage and Current Waveforms

Inputs Active and Inactive Times

Voltage Waveforms - Propagation Delay Times

Figure 1 - Parameter Measurement Information (V

DDQ = 2.5V ±0.2V)

Voltage Waveforms - Pulse Duration

Voltage Waveforms - Setup and Hold Times

VDDQ

VIH

VOH

VTT

VOH

VIH

VIL

VOL

VI(pp)

VIL

VREF

VICR

tPHL

V/2

VICR

Input

Timing

Input

Timing

Input

Output

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