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HCS08 Datasheet(PDF) 151 Page - NXP Semiconductors

No. de pieza HCS08
Descripción Electrónicos  Microcontrollers
PDF  316 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
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HCS08 Datasheet(HTML) 151 Page - NXP Semiconductors

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Internal Clock Source (S08ICSV2)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
151
10.1.4.4
FLL Bypassed Internal Low Power (FBILP)
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
10.1.4.5
FLL Bypassed External (FBE)
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
10.1.4.6
FLL Bypassed External Low Power (FBELP)
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
10.1.4.7
Stop (STOP)
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
10.2
External Signal Description
There are no ICS signals that connect off chip.
10.3
Register Definition
Figure 10-1 is a summary of ICS registers.
Table 10-1. ICS Register Summary
Name
76543
2
1
0
ICSC1
R
CLKS
RDIV
IREFS
IRCLKEN
IREFSTEN
W
ICSC2
R
BDIV
RANGE
HGO
LP
EREFS
ERCLKEN
EREFSTEN
W
ICSTRM
R
TRIM
W
ICSSC
R
0
0
0
IREFST
CLKST
OSCINIT
FTRIM
W



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