HCS08 datasheet(185/316 Pages) NXP

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Modulo Timer (S08MTIMV1)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

185

12.3.2

MTIM Clock Configuration Register (MTIMCLK)

MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS).

432

CLKS

Reset:

Figure 12-5. MTIM Clock Configuration Register

Table 12-3. MTIM Clock Configuration Register Field Description

Field

Description

7:6

Unused register bits, always read 0.

5:4

CLKS

Clock Source Select — These two read/write bits select one of four different clock sources as the input to the

MTIM prescaler. Changing the clock source while the counter is active does not clear the counter. The count

continues with the new clock source. Reset clears CLKS to 000.

Encoding 0. Bus clock (BUSCLK)

Encoding 1. Fixed-frequency clock (XCLK)

Encoding 3. External source (TCLK pin), falling edge

Encoding 4. External source (TCLK pin), rising edge

All other encodings default to the bus clock (BUSCLK).

3:0

Clock Source Prescaler — These four read/write bits select one of nine outputs from the 8-bit prescaler. Changing

the prescaler value while the counter is active does not clear the counter. The count continues with the new

prescaler value. Reset clears PS to 0000.

0000 Encoding 0. MTIM clock source

 1

0001 Encoding 1. MTIM clock source

 2

0010 Encoding 2. MTIM clock source

 4

0011 Encoding 3. MTIM clock source

 8

0100 Encoding 4. MTIM clock source

 16

0101 Encoding 5. MTIM clock source

 32

0110 Encoding 6. MTIM clock source

 64

0111 Encoding 7. MTIM clock source

 128

1000 Encoding 8. MTIM clock source

 256

All other encodings default to MTIM clock source

 256.

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