Z84C9012VSC datasheet(21/31 Pages) ZILOG

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Z84C90

KIO Serial/Parallel Counter Timer

PS011802-0902

TsIEI(Cf)

IEI to Clock Fall Setup (for 4D

Decode)

TsIOr(Cf)

IORQ Rise to Clock Fall Setup

(to activate RDY on next clock)

100

PIO Timing

TdCf(RDYr)

Clock Fall to RDY Rise Delay

100

TdCf(RDYf)

Clock Fall to RDY Fall Delay

100

TwSTB

STB Pulse Width

100

TsSTBr(Cf)

STB Rise to Clock Fall Setup

(to activate RDY on next clock

cycle)

100

TdIOf(PD)

IORQ Fall to Port Data Valid

(Mode 0)

140

120

TsPD(STBr)

Port A,B Data to STB Rise Setup

Time (Mode 1)

140

TdSTBI(PD)

STB Fall to Port A,B Data Valid

Delay (Mode 2)

150

120

TdSTBr(PDz)

STB Rise to Port Data Float Delay

(Mode 2)

140

120

TdPD(INTf)

Port Data Match to INT Fall Delay

(Mode 3)

250

200

TdSTBr(INTf)

STB Rise to INT Fall Delay

290

220

TsPD(RIf)

PIA Port Data to RD, IORQ Fall

Setup

TBD

–

TdCr(PD)

Clock Rise to Port Data Valid Delay

CTC Timing

TdCr(INTf)

Clock Rise to INT Rise Delay

TcC+100

TcC+80

TsCTRr(Cr)c

CLK/TRG Rise to Clock Rise Setup

(for immediate count, Counter

mode)

TsCTRr(Cr)t

CLK/TRG Rise to Clock Rise Setup

(for enabling prescaler on following

Clock Rise, Timer mode)

Table 5. AC Characteristics of the Z84C90 (Continued)

8MHz

10MHz1

12MHz

No. Symbol

Parameter

Min

Max

Min

Max

Min Max U/M

Z84C9012VSC Datasheet(PDF) 21 Page - Zilog, Inc.

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