ADP5062ACPZ-1-R7 datasheet(41/44 Pages) AD

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Data Sheet

ADP5062

Rev. B | Page 41 of 44

I2C REGISTER DEFAULTS

Table 46. I2C Register Default Settings

Bit Name

I2C Register Address, Bit Location

Option

Selection

CHG_VLIM[1:0]

Address 0x03, Bits[1:0]

0 = limit 3.2 V

1 = limit 3.7 V

DIS_RCH

Address 0x05, Bit 7

0 = recharge enabled

1 = recharge disabled

EN_WD

Address 0x06, Bit 2

0 = watchdog disabled

0 = disabled

1 = watchdog enabled

DIS_IC1

Address 0x07, Bit 6

0 = not activated

1 = activated

EN_CHG

Address 0x07, Bit 0

0 = charging disabled

1 = charging enabled

EN_JEITA

Address 0x08, Bit 7

0 = JEITA disabled

1 = JEITA enabled

JEITA_SELECT

Address 0x08, Bit 6

0 = JEITA1 charging

1= JEITA2 charging

EN_CHG_VLIM

Address 0x08, Bit 5

0 = limit disabled

1 = limit enabled

IDEAL_DIODE[1:0]

Address 0x08, Bits[4:3]

00 = ideal diode operates when VISO_Sx < VISO_Bx

00 = VISO_Sx < VISO_Bx

01 = ideal diode operates when VISO_Sx < VISO_Bx

and VBAT_SNS > VWEAK

10 = ideal diode is disabled

11 = ideal diode is disabled

DIGITAL INPUT AND OUTPUT OPTIONS

Table 47. I2C Address 0x11, Bits[1:0] SYS_EN Output Default

Option

Selection (Default)

00 = SYS_EN is activated when LDO is active and system voltage is available

01 = SYS_EN is activated by ISO_Bx voltage; battery charging mode

10 = SYS_EN is activated and the isolation FET is disabled when the battery drops below VWEAK1

11 = SYS_EN is active in LDO mode when the charger is disabled. SYS_EN is active in charging mode when VISO_Bx ≥ VWEAK

This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit D5 (EN_BMON).

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