ADP2165ACPZ-2.5-R7 datasheet(12/23 Pages) AD

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ADP2165/ADP2166

Data Sheet

Rev. B | Page 12 of 23

THEORY OF OPERATION

The ADP2165/ADP2166 are step-down, dc-to-dc regulators.

They use a current mode architecture with an integrated high-side

and low-side switch. They target high performance applications

that require high efficiency and design simplicity.

The ADP2165/ADP2166 can operate with an input voltage from

2.7 V to 5.5 V and regulate the output voltage down to 0.6 V.

Additional features for flexible design include programmable

switching frequency, programmable soft start, external

compensation, and enable and power-good pins. The

ADP2165/ADP2166 are also available with preset output

voltage options of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V.

CONTROL SCHEME

The ADP2165/ADP2166 use a fixed frequency, current mode

PWM control architecture for good line and load transient

performance. In fixed frequency PWM mode, adjust the duty

cycle of the integrated MOSFET to regulate the output voltage

that has a low output ripple voltage.

PWM MODE

At the start of each oscillator cycle, the high-side NFET (N-

channel MOSFET) switch turns on and transmits a positive

voltage across the inductor. Current in the inductor increases

until the current sense signal crosses the peak inductor current

level set by the voltage on the COMP pin. The high-side NFET

then turns off, and the low-side NFET synchronous rectifier

then turns on. This puts a negative voltage across the inductor,

causing the inductor current to decrease. The synchronous

rectifier stays on for the rest of the cycle.

ENABLE/SHUTDOWN

The EN input pin has a precision analog threshold of 1.2 V

(typical) with 100 mV of hysteresis. When the enable voltage

exceeds 1.2 V, the regulator turns on, and when it falls below

1.1 V (typical), the regulator turns off. To force the devices to

automatically start when input power is applied, connect the EN

pin to the PVIN pin.

When the ADP2165/ADP2166 are shut down, the soft start

capacitor discharges. When the devices are reenabled, a new

soft start cycle begins.

If the EN pin is not externally connected, an internal pull-down

resistor (1 MΩ) prevents an accidental enable.

INTERNAL REGULATOR (VREG)

The internal regulator provides a stable supply for the internal

control circuits. It is recommended to place a 1 μF ceramic

capacitor between the VREG and GND pins. The internal

regulator also includes a current-limit circuit to protect the

circuit if the maximum external load is added.

The AVIN pin provides the power supply for the internal regulator.

When device is enabled, the internal regulator is active.

BOOTSTRAP CIRCUITRY

The ADP2165/ADP2166 integrate the boot regulator to provide

the gate drive voltage for the high-side NFET. A capacitor between

the BST and SW pins is charged from the PVIN pin while the

low-side NFET is on.

Placing an X7R or X5R 0.1 μF ceramic capacitor between the

BST and SW pins is recommended.

OSCILLATOR AND SYNCHRONIZATION

The switching frequency of the ADP2165/ADP2166 can be set

by connecting a resistor between the RT pin and the GND pin.

Use the following equation to set the switching frequency:

RRT (kΩ) = 60,000/[fSW (kHz) + 10] − 5

A 191 kΩ resistor sets the frequency to 300 kHz, and a 93.1 kΩ

resistor sets frequency to 600 kHz. Figure 29 shows the typical

relationship between RRT and fSW.

1600

1400

1200

1000

800

600

200

400

180

160

140

120

100

RRT (kΩ)

Figure 29. Frequency (fSW) vs. RT Resistor

To synchronize the ADP2165/ADP2166, drive an external clock

at the SYNC pin. The frequency of the external clock can be in

the 250 kHz to 1.4 MHz range.

During the synchronization, the RT pin can be used to program

the phase shift. When the RT pin is connected to the VREG pin,

the rising edge of the SW pin is 180° out of phase with the external

clock. If the RT pin is floating, the rising edge of the SW pin is in

phase with the external clock.

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