STM32G070CB datasheet(21/93 Pages) STMICROELECTRONICS

21 / 93 page

DS12766 Rev 2

21/93

STM32G070CB/KB/RB

Functional overview

Features of the NVIC:



Low-latency interrupt processing



4 priority levels



Handling of a non-maskable interrupt (NMI)



Handling of 32 maskable interrupt lines



Handling of 10 Cortex-M0+ exceptions



Later-arriving higher-priority interrupt processed first



Tail-chaining



Interrupt vector retrieval by hardware

3.13.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and

allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising,

and falling edge detector capability. Any GPIO and a few peripheral signals can be

connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which allows the

software to identify the origin of the processor's wake-up from Stop mode or, to identify the

GPIO and the edge event having caused an interrupt.

3.14

Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32G070CB/KB/RB

devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC

has up to 16 external channels and 3 internal channels (temperature sensor, voltage

reference, VBAT monitoring). It performs conversions in single-shot or scan mode. In scan

mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling

rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that

the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole VDD supply

range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to

16 bits (refer to AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all scanned channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to

the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

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