SN54HC259, SN74HC259

8BIT ADDRESSABLE LATCHES

SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

2

POST OFFICE BOX 655303

description/ordering information (continued)

Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the

addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch

follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all

latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the

possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines

are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the

D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data

inputs.

Function Tables

FUNCTION

INPUTS

OUTPUT OF

ADDRESSED

EACH

OTHER

FUNCTION

CLR

G

ADDRESSED

LATCH

OTHER

OUTPUT

FUNCTION

H

L

D

QiO

Addressable latch

H

HQiO

QiO

Memory

L

LD

L

8-line demultiplexer

L

H

L

L

Clear

LATCH SELECTION

SELECT INPUTS

LATCH

S2

S1

S0

LATCH

ADDRESSED

L

L

L

0

L

LH

1

L

HL

2

L

HH

3

H

LL

4

H

LH

5

H

HL

6

H

H

H

7