DLPC4430 datasheet(4/49 Pages) TI

4 / 49 page

Table 5-1. Pin Functions

PIN(1)

I/O(2)

DESCRIPTION

NAME

NO.

POSENSE

P22

Power-On Sense, High true, signal provided from an external voltage monitor circuit. This signal is driven active

(high) when all ASIC supply voltages have reached 90% of their specified minimum voltage. This signal is driven

inactive (low) after the falling edge of PWRGOOD as specified.

PWRGOOD

T26

Power Good, High true, signal from external power supply or voltage monitor. A high value indicates all power is

within operating voltage specs and the system is safe to exit its reset state. A transition from high to low is used

to indicate that the controller or DMD supply voltage drops below their rated minimum level. This transition must

occur prior to the supply voltage drop as specified. During this interval, POSENSE must remain active high. This is a

warning of an imminent power loss condition. This warning is required to enhance long term DMD reliability. A DMD

park followed by a full controller reset is performed by the DLPC4430 controller when PWRGOOD goes low for the

specified minimum, protecting the DMD. This minimum de-assertion time is used to protect the input from glitches.

Following this the DLPC4430 controller is held in its reset state as long as PWRGOOD is low. PWRGOOD must be

driven high for normal operation. The DLPC4430 controller acknowledges PWRGOOD as active once it has been

driven high for a specified minimum time. Uses hysteresis.

EXT_ARTZ

T24

General purpose, LOW true, reset output. This output is asserted low immediately upon asserting power-up reset

(POSENSE) low and remains low while POSENSE remains low. EXT_ARSTZ continues to be held low after the

release of power-up reset (that is, POSENSE set high) until released by software. EXT_ARSTZ is also asserted low

approximately 5µs after the detection of a PWRGOOD or any internally generated reset. In all cases it remains active

for a minimum of 2ms. Note that the ASIC contains a software register that can be used to independently drive this

output.

MTR_ARTZ

T25

Color wheel motor controller, LOW true, reset output. This output is asserted low immediately upon asserting

power-up reset (POSENSE) low and remains low while POSENSE remains low. MTR_ARSTZ continues to be held

low after the release of power-up reset (i.e. POSENSE set high) until released by software. MTR_ARSTZ is also

optionally asserted low approximately 5 µs after the detection of a PWRGOOD or any internally generated reset. In

all cases it remains active for a minimum of 2 ms. Note that the ASIC contains a software register that can be used to

independently drive this output. The ASIC also contains a software register that can be used to disable the assertion

of motor reset upon a lamp strike reset.

BOARD LEVEL TEST AND INITIALIZATION (3)

TDI

N25

JTAG serial data in

TCK

N24

JTAG serial data clock

TMS1

P25

JTAG test mode select

TMS2

P26

JTAG test mode select

TDO1

N23

JTAG serial data out

TDO2

N22

JTAG serial data out

TRSTZ

M23

JTAG reset. This signal includes an internal pull-up and utilizes hysteresis. This pin is pulled high (or left

unconnected) when the JTAG interface is in use for boundary scan or ARM debug. Connect this pin to ground

otherwise. Failure to tie this pin low during normal operation will cause startup and initialization problems.

RTCK

JTAG Return Clock

ETM_PIPESTAT_2

ETM Trace Port Pipeline Status. Indicates the pipeline status of the ARM core. These signals include internal

pull-downs.

ETM_PIPESTAT_1

ETM_PIPESTAT_0

ETM_TRACESYNC

ETM Trace Port Synchronization signal, indicating the start of a branch sequence on the trace packet port. This

signal includes an internal pull-down.

ETM_TRACECLK

ETM Trace Port Clock. This signal includes an internal pull-down.

ICTSEN

M24

IC Tri-State Enable (active high). Asserting high will Tri-state all outputs except the JTAG interface. This signal

includes an internal pull-down, however an external pull-down is recommended for added protection. Uses

hysteresis.

TSTPT_7

Test pin 7 - This signal provides internal pull-downs.