STM32WL55JC datasheet(36/147 Pages) STMICROELECTRONICS

36 / 147 page

Functional overview

STM32WL55/54xx

36/147

DS13293 Rev 2

3.13

Reset and clock controller (RCC)

The following different clock sources can be used to drive the system clock (SYSCLK):

•

HSI16 (high-speed internal) 16 MHz RC oscillator clock

•

MSI (multi-speed internal) RC oscillator clock from 100 kHz to 48 MHz

•

HSE32 (high-speed external) 32 MHz oscillator clock, with trimming capacitors.

•

PLL clock

The MSI is used as system clock source after startup from reset, configured at 4 MHz.

The devices have the following additional clock sources:

•

LSI: 32 kHz low-speed internal RC that may drive the independent watchdog and

optionally the RTC used for auto-wakeup from Stop and Standby modes.

•

LSE: 32.768 kHz low-speed external crystal that optionally drives the RTC used for

auto-wakeup from Stop, Standby and Shutdown modes, or the real-time clock

(RTCCLK).

Each clock source can be switched on or off independently when it is not used, to optimize

power consumption.

Several prescalers can be used to configure the AHB frequencies (HCLK3/PCLK3, HCLK1,

HCLK2), the high-speed APB2 (PCLK2) and the low-speed APB1 (PCLK1) domains. The

maximum frequency of the AHB (HCLK3, HCLK1, and HCLK2), the PCLK1 and the PCLK2

domains is 48 MHz.

Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except the following:

•

The clock used for true RNG, is derived (selected by software) from one of the following

sources:

–

PLL VCO (PLLQCLK) (only available in Run mode)

–

MSI (only available in Run mode)

–

LSI clock

–

LSE clock

•

The ADC clock is derived (selected by software) from one of the following sources:

–

system clock (SYSCLK) (only available in Run mode)

–

HSI16 clock (only available in Run mode)

–

PLL VCO (PLLPCLK) (only available in Run mode)

•

The DAC uses the LSI clock in sample and hold mode

•

The (LP)U(S)ARTs clocks are derived (selected by software) from one of the following

sources:

–

system clock (SYSCLK) (only available in Run mode)

–

HSI16 clock (available in Run and Stop modes)

–

LSE clock (available in Run and Stop modes)

–

APB clock (PCLK depending on which APB the U(S)ART is mapped) (available in

CRun and CSleep when also enabled in (LP)U(S)ARTxSMEN)

The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.

STM32WL55JC Datasheet(PDF) 36 Page - STMicroelectronics

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