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2015-08-0013

PT0572

09/24/15

28

PI5USB2546Q

USB Charging Port Controller and Load Detection Power Switch

Application Information

Input and Output Capacitance

Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular

application. For all applications, a 0.1uF or greater ceramic bypass capacitor between IN and GND is recommended as close to the

device as possible for local noise decoupling. This precaution reduces ringing on the input due to power-supply transients.

Additional input capacitance may be needed on the input to reduce voltage overshoot from exceeding the absolute-maximum

voltage of the device during heavy transient conditions or output shorting. This is especially important during bench testing when

long inductive cables are used to connect the evaluation board to the bench power supply. Normally suggested the distance

between IC and DC supply is less than 15cm.

Output capacitance also need to be close to IC as possible. When large transient currents are expected on the output，placing a

high-value electrolytic capacitor on the output pin is recommended,

Layout Design Guideline

1.

The PCB is suggested to use at least 4 layers

2.

The high speed differential pair should be maintain 90Ω

3.

Do not route the high speed signal over any split plane

4.

Minimized the number of vias and corners on the high speed trace for reducing the signal reflections and impedance

changes

5.

If it’s necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°turn. This can reduces reflections on

the signal by minimizing impedance discontinuities.

6.

The high speed trace should be routed symmetrically and parallelism (including the test points on the high speed trace).

The non-parallelism trace will cause the impedance discontinuities and affect the signal quality

7.

Avoid any unnecessary stubs on the differential pair. The stubs will introduce the signal reflections which affect the signal

quality

8.

Avoid routing the high speed differential pair under the crystal, oscillator, clock synthesizer, magnetic devices or ICs to

cause the interference.

9.

Avoid anti-etch on the GND plane

Typical Application Circuit

ILIM_SEL

EN

STATUS#

FAULT#

USB Host

VBUS_OUT

R1

80.6k

R2

22k

U1

PI5USB2546ZHE@TQFN16

IN

1

DM_OUT

2

3

DP_OUT

ILIM_SEL

4

STATUS#

9

DP_IN

10

DM_IN

11

OUT

12

USB

Connector

Differential

C1

0.1uF

R3

10k

C3

120uF

C2

10uF

VBUS_IN

VBUS

D-

D+

GND

DC Power

BUS

R4

10k

uP