AX5043 datasheet(21/47 Pages) ONSEMI

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AX5043

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Packet Modes

The AX5043 offers different packet modes. For arbitrary

packet sizes HDLC is recommended since the flag and

bit−stuffing mechanism. The AX5043 also offers packet

modes with fixed packet length with a byte indicating the

length of the packet.

In packet modes a CRC can be computed automatically.

HDLC Mode is the main framing mode of the AX5043. In

this mode, the AX5043 performs automatic packet

delimiting, and optional packet correctness check by

inserting and checking a cyclic redundancy check (CRC)

field.

NOTE: HDLC mode follows High−Level Data Link

Control (HDLC, ISO 13239) protocol.

The packet structure is given in the following table.

Table 20. HDLC PACKET STRUCTURE

Flag

Address

Control

Information

FCS

(Optional Flag)

8 bit

8 or 16 bit

Variable length, 0 or more bits in multiples of 8

16 / 32 bit

8 bit

HDLC packets are delimited with flag sequences of

content 0x7E.

In AX5043 the meaning of address and control is user

defined. The Frame Check Sequence (FCS) can be

programmed to be CRC−CCITT, CRC−16 or CRC−32.

The receiver checks the CRC, the result can be retrieved

from the FIFO, the CRC is appended to the received data.

In Wireless M−Bus Mode, the packet structure is given in

the following table.

NOTE: Wireless M−Bus mode follows EN13757−4

Table 21. WIRELESS M−BUS PACKET STRUCTURE

Preamble

FCS

Optional Data Block

(optionally repeated with FCS)

FCS

variable

8 bit

16 bit

48 bit

16 bit

8 − 96 bit

16 bit

For details on implementing a HDLC communication as

well as Wireless M−Bus please use the AXSEM RadioLab

software and see the AX5043 Programming Manual.

Raw Modes

In Raw mode, the AX5043 does not perform any packet

delimiting or byte synchronization. It simply serializes

transmit bytes and de−serializes the received bit−stream and

groups it into bytes. This mode is ideal for implementing

legacy protocols in software.

Raw mode with preamble match is similar to raw mode.

In this mode, however, the receiver does not receive

anything until it detects a user programmable bit pattern

(called the preamble) in the receive bit−stream. When it

detects the preamble, it aligns the de−serialization to it.

The preamble can be between 4 and 32 bits long.

RX AGC and RSSI

AX5043 features three receiver signal strength indicators

(RSSI):

1. RSSI before the digital IF channel filter.

The gain of the receiver is adjusted in order to

keep the analog IF filter output level inside the

working range of the ADC and demodulator. The

value of the AGC and can be used as an RSSI. The

step size of this RSSI is 0.625 dB. The value can

be used as soon as the RF frequency generation

sub−system has been programmed.

2. RSSI behind the digital IF channel filter.

The register RSSI contains the current value of the

RSSI behind the digital IF channel filter. The step

size of this RSSI is 1 dB.

3. RSSI behind the digital IF channel filter high

accuracy.

The demodulator also provides amplitude

information in the TRK_AMPLITUDE register.

By combining both the AGCCOUNTER and the

TRK_AMPLITUDE registers, a high resolution

(better than 0.1 dB) RSSI value can be computed

at the expense of a few arithmetic operations on

the micro−controller. The AXSEM RadioLab

Software calculates the necessary register settings

for best performance and details can be found in

the AX5043 Programming Manual.

Modulator

Depending on the transmitter settings the modulator

generates various inputs for the PA:

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