25CSM04 datasheet(2/55 Pages) MICROCHIP

2 / 55 page

25CSM04

DS20005817D-page 2

 2019-2022 Microchip Technology Inc. and its subsidiares

General Description

The Microchip Technology Inc. 25CSM04 provides

4-Mbits of Serial EEPROM utilizing the Serial

Peripheral Interface (SPI) compatible bus. The device

is organized as 524,288 bytes of 8 bits each

(512 Kbyte) and is optimized for use in consumer and

industrial applications where reliable and dependable

nonvolatile

memory

storage

essential. The

25CSM04 is capable of operation across a broad

voltage range (2.5V to 5.5V).

The bus signals required are a clock input (SCK) plus

separate data in (SI) and data out (SO) lines. Access to

the device is controlled through a Chip Select (CS)

input. Communication to the device can be paused via

the HOLD pin. While the device is paused, transitions

on its inputs will be ignored, with the exception of Chip

Select, allowing the host to service higher priority

interrupts.

The 25CSM04 features a nonvolatile Security register

independent of the 4 Mbit main memory array. The first

half of the Security register is read-only and contains a

factory-programmed, globally unique 128-bit serial

number in the first 16 bytes. The 128-bit serial number

is unique across the entire CS series of Serial

EEPROM products and eliminates the time consuming

step of performing and ensuring serialization of a

product on a manufacturing line. The 128-bit read-only

serial number is followed by an additional 256 bytes of

user-programmable EEPROM.

The user-programmable section of the Security

software sequence.

The 25CSM04 features a configurable write protection

scheme which allows the user to select Legacy Write

Protection mode or Enhanced Write Protection mode.

Legacy Write Protection mode enables the Block

Protection function via the STATUS register. Enhanced

Write Protection mode segments the memory into

independent

partitions.

Each

partition

can

configured to inhibit writing based on the status of the

Memory Partition register setting.

For added reliability the 25CSM04 uses a built-in Error

Correction Code (ECC) scheme. This scheme can

correct up to one incorrectly read bit within four bytes

read out. Additionally, the 25CSM04 includes a flag in

the STATUS register to report if any errors were

detected and corrected in the most recent memory

array read sequence.

The 25CSM04 features an identification register that

contains identification information that can be read

from the device. This enables the application to

electronically query and identify the 25CSM04 while it

is in the system. The identification method and the

instruction opcode comply with the JEDEC® standard

for “Manufacturer and Device ID Read Methodology for

SPI Compatible Serial Interface Memory Devices”. The

type of information that can be read from the device

includes the JEDEC defined Manufacturer ID, the

vendor-specific Device ID, and the vendor-specific

Extended Device Information (EDI).

Bus Connections for the 25CSM04

Client 0

Client 1

Client 2

Client 3

25CSM04 Datasheet(PDF) 2 Page - Microchip Technology

25CSM04 Datasheet(HTML) 2 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Descarga

Enlace URL