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FXLS8964AF Datasheet(PDF) 41 Page - NXP Semiconductors |
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FXLS8964AF Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer Bit 7 6 5 4 3 2 1 0 Name BUF_Y[11:4] Reset — — — — — — — — Access R R R R R R R R Table 40. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_CONFIG2[LE_BE] = 1 bit allocation Bit 7 6 5 4 3 2 1 0 Name BUF_Y[3:0] 0 0 0 0 Reset — — — — — — — — Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Name BUF_Z[11:4] Reset — — — — — — — — Access R R R R R R R R Table 41. BUF_Z_LSB and BUF_Z_MSB registers (addresses 10h, 11h) with SENS_CONFIG2[LE_BE] = 1 bit allocation Bit 7 6 5 4 3 2 1 0 Name BUF_Z[3:0] 0 0 0 0 Reset — — — — — — — — Access R R R R R R R R 15.8 PROD_REV register (address 12h) The register contains the product revision number. The revision number is stored in BCD format, as MAJ.MIN with a range from 1.0 to 9.9, with the initial silicon revision reporting revision 1.0 (10h). Bit 7 6 5 4 3 2 1 0 Name PROD_REV_MAJ[3:0] PROD_REV_MIN[3:0] Reset 0 0 0 1 0 0 1 1 Access R R R R R R R R Table 42. PROD_REV register (address 12h) bit allocation Field Description 7 to 4 PROD_REV_MAJ[3:0] Product revision info, major product revision value with range 1 to 9 in BCD format. 3 to 0 PROD_REV_MIN[3:0] Product revision info, minor product revision value with range 0 to 9 in BCD format. Table 43. PROD_REV register (address 12h) bit description FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.4 — 7 December 2021 41 / 98 |
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