STM32F405 datasheet(113/204 Pages) STMICROELECTRONICS

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DS8626 Rev 9

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STM32F405xx, STM32F407xx

Electrical characteristics

Static latchup

Two complementary static tests are required on six parts to assess the latchup

performance:

•

A supply overvoltage is applied to each power supply pin

•

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

5.3.15

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product

operation. However, in order to give an indication of the robustness of the microcontroller in

cases when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of

μA/+0 μA range), or other functional failure (for example reset, oscillator frequency

deviation).

Negative induced leakage current is caused by negative injection and positive induced

leakage current by positive injection.

The test results are given in Table 47.

2. On VBAT pin, VESD(HBM) is limited to 1000 V.

Table 46. Electrical sensitivities

Symbol

Parameter

Conditions

Class

Static latch-up class

TA = +105 °C conforming to JESD78A

II level A

STM32F405 Datasheet(PDF) 113 Page - STMicroelectronics