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DVR Datasheet(PDF) 134 Page - Microchip Technology

No. de pieza DVR
Descripción Electrónicos  16-Bit General Purpose Microcontrollers with 256-Kbyte Flash and 16-Kbyte RAM in Low Pin Count Packages
PDF  416 Pages
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Fabricante Electrónico  MICROCHIP [Microchip Technology]
Página de inicio  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DVR Datasheet(HTML) 134 Page - Microchip Technology

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PIC24FJ256GA705 FAMILY
DS30010118D-page 134
 2016-2018 Microchip Technology Inc.
REGISTER 11-10: IOCFx: INTERRUPT-ON-CHANGE FLAG x REGISTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCFx<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCFx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
IOCFx<15:0>: Interrupt-on-Change Flag x bits
1 = An enabled change was detected on the associated pin; set when IOCPx = 1 and a positive edge was
detected on the IOCx pin, or when IOCNx = 1 and a negative edge was detected on the IOCx pin
0 = No change was detected or the user cleared the detected change
Note 1:
It is not possible to set the IOCFx register bits with software writes (as this would require the addition of
significant logic). To test IOC interrupts, it is recommended to enable the IOC functionality on one or more
GPIO pins and then use the corresponding LATx register bit(s) to trigger an IOC interrupt.
2:
See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-11: IOCPUx: INTERRUPT-ON-CHANGE PULL-UP ENABLE x REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCPUx<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCPUx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
IOCPUx<15:0>: Interrupt-on-Change Pull-up Enable x bits
1 = Pull-up is enabled
0 = Pull-up is disabled
Note 1:
See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.



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