SPSB081 datasheet(94/135 Pages) STMICROELECTRONICS

94 / 135 page

Bit

Name

Description

1 = CAN Trx Active Mode

At Exit from Active Mode, this bit is set to ‘0’ automatically

LIN_WU_EN(2)

Enable wake-up by LIN

0 = disabled

1 = enabled (default)

Note:

The wake-up behavior is configurable in the Configuration Register (0x3F)

CAN_WU_EN (2)

CAN Receive only Mode

0 CAN Receive Only Mode disabled (default)

1 CAN Receive Only Mode enabled (CAN Trx must be activated, see CAN_ACT bit)

TIMER_NINT _SEL

CAN Transceiver activation

0 = CAN Trx Low Power Mode (default)

1 = CAN Trx Active Mode

At Exit from Active Mode, this bit is set to ‘0’ automatically

TIMER_WU _EN

Enable wake-up by LIN

0 = disabled

1 = enabled (default)

Note:

The wake-up behavior is configurable in the Configuration Register (0x3F)

TRIG

CAN Receive only Mode

0 CAN Receive Only Mode disabled (default)

1 CAN Receive Only Mode enabled (CAN Trx must be activated, see CAN_ACT bit)

1. Lower is the timer duration and major is the contribution of output tdON

2. For SPSB0815 and SPSB0813 either LIN, CAN or WUx must be enabled as wake-up source. For

SPSB081C devices (without LIN), the LIN_WU_EN is forced to 0. If DIR_WU2_EN is set to 0, setting

all bits 3, 4, 16 & 17 to ‘0’ is an invalid setting. If DIR_WU2_EN is set to 1, setting all bits 3, 4, 16 to ‘0’ is an

invalid setting. In case of invalid setting, all wake-up sources will be configured according to default setting

and SPI Error Bit (SPIE) in Global Status Register will be set.

Table 73. Control register CR2 (0x02)

Bit

name

Access

0 (R)

0 (R/W)

0 (R)

0 (R/W)

(R/

0 (R/W)

Table 74. CR2 signals description

Bit

Name

Description

RES

Reserved

RES

Reserved

T2 ON_2

Configuration of Timer 2 on-time(1):

0 0 0 ton1 (default)

T2 ON_1

SPSB081

Control registers

DS14048 - Rev 1

page 94/135

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