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TC74ACT74FN Datasheet(PDF) 1 Page - Toshiba Semiconductor |
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TC74ACT74FN Datasheet(HTML) 1 Page - Toshiba Semiconductor |
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1 / 11 page ![]() TC74ACT74P/F/FN/FT 2006-02-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT74P,TC74ACT74F,TC74ACT74FN,TC74ACT74FT Dual D-Type Flip Flop with Preset and Clear The TC74ACT74 is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an “L” level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: fmax = 180 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 µA (max) at Ta = 25°C • Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines. • Balanced propagation delays: tpLH ∼− tpHL • Pin and function compatible with 74F74 Weight DIP14-P-300-2.54 : 0.96 g (typ.) SOP14-P-300-1.27A : 0.18 g (typ.) SOP14-P-300-1.27 : 0.18 g (typ.) SOL14-P-150-1.27 : 0.12 g (typ.) TSSOP14-P-0044-0.65A : 0.06 g (typ.) Note: xxxFN (JEDEC SOP) is not available in Japan. TC74ACT74P TC74ACT74F TC74ACT74FN TC74ACT74FT |
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