MPC8540 datasheet(7/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

vii

Contents

Paragraph

Number

Title

Page

Number

2.3.6

Device-Specific Utilities............................................................................................ 2-15

2.4

Complete CCSR Map .................................................................................................... 2-16

Chapter 3

Signal Descriptions

3.1

Signals Overview .............................................................................................................3-1

3.2

Configuration Signals Sampled at Reset ....................................................................... 3-15

3.3

Output Signal States During Reset ................................................................................ 3-16

Chapter 4

Reset, Clocking, and Initialization

4.1

Overview.......................................................................................................................... 4-1

4.2

External Signal Descriptions ........................................................................................... 4-1

4.2.1

System Control Signals................................................................................................ 4-2

4.2.2

Clock Signals ............................................................................................................... 4-3

4.3

Memory Map/Register Definition ................................................................................... 4-3

4.3.1

Local Configuration Control........................................................................................ 4-3

4.3.1.1

Accessing Configuration, Control, and Status Registers......................................... 4-4

4.3.1.1.1

Updating CCSRBAR ........................................................................................... 4-4

4.3.1.1.2

Configuration, Control, and Status Base Address Register

(CCSRBAR) .................................................................................................... 4-5

4.3.1.2

Accessing Alternate Configuration Space ............................................................... 4-5

4.3.1.2.1

Alternate Configuration Base Address Register (ALTCBAR)............................ 4-6

4.3.1.2.2

Alternate Configuration Attribute Register (ALTCAR)...................................... 4-6

4.3.1.3

Boot Page Translation.............................................................................................. 4-7

4.3.1.3.1

Boot Page Translation Register (BPTR).............................................................. 4-8

4.3.2

Boot Sequencer ............................................................................................................ 4-8

4.4

Functional Description..................................................................................................... 4-8

4.4.1

Reset Operations .......................................................................................................... 4-8

4.4.1.1

Soft Reset................................................................................................................. 4-9

4.4.1.2

Hard Reset ...............................................................................................................4-9

4.4.2

Power-On Reset Sequence........................................................................................... 4-9

4.4.3

Power-On Reset Configuration.................................................................................. 4-11

4.4.3.1

System PLL Ratio.................................................................................................. 4-12

4.4.3.2

e500 Core PLL Ratio ............................................................................................. 4-13

4.4.3.3

Boot ROM Location .............................................................................................. 4-14

4.4.3.4

Host/Agent Configuration ..................................................................................... 4-14

4.4.3.5

CPU Boot Configuration ....................................................................................... 4-15

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