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STM32W108CB Datasheet(PDF) 144 Page - STMicroelectronics

No. de pieza STM32W108CB
Descripción Electrónicos  High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory
PDF  278 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32W108CB Datasheet(HTML) 144 Page - STMicroelectronics

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Serial interfaces
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
144/278
Doc ID 16252 Rev 14
9.12.9
Serial controller receive DMA counter channel A register
(SCx_DMARXCNTAR)
Address offset: 0xC820 (SC1_DMARXCNTAR) and 0xC020 (SC2_DMARXCNTAR)
Reset value:
0x0000 0000
Reserved, must be kept at reset value
CNT[12:0]:
9.12.10
Serial controller receive DMA count channel B register
(SCx_DMARXCNTBR)
Address offset: 0xC824 (SC1_DMARXCNTBR) and 0xC024 (SC2_DMARXCNTBR)
Reset value:
0x0000 0000
Reserved, must be kept at reset value
CNT[12:0]:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CNT[12:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits [31:13]
Bits [12:0]
The offset from the start of DMA receive buffer A at which the next byte is written. This
register is set to zero when the buffer is loaded and when the DMA is reset. If this register is
written when the buffer is not loaded, the buffer is loaded.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CNT[12:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits [31:13]
Bits [12:0]
The offset from the start of DMA receive buffer B at which the next byte is written. This
register is set to zero when the buffer is loaded and when the DMA is reset. If this register is
written when the buffer is not loaded, the buffer is loaded.



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