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STM32W108CB Datasheet(PDF) 149 Page - STMicroelectronics |
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STM32W108CB Datasheet(HTML) 149 Page - STMicroelectronics |
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149 / 278 page  STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Serial interfaces Doc ID 16252 Rev 14 149/278 9.12.14 Serial controller receive DMA channel A first error register (SCx_DMARXERRAR) Address offset: 0xC834 (SC1_DMARXERRAR) and 0xC034 (SC2_DMARXERRAR) Reset value: 0x0000 0000 Reserved, must be kept at reset value ADD[12:0]: 9.12.15 Serial controller receive DMA channel B first error register (SCx_DMARXERRBR) Address offset: 0xC838 (SC1_DMARXERRBR) and 0xC038 (SC2_DMARXERRBR) Reset value: 0x0000 0000 Reserved, must be kept at reset value ADD[12:0]: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ADD[12:0] r r r r r rr rr rr r r Bits [31:13] Bits [12:0] The offset from the start of DMA receive buffer A of the first byte received with a parity, frame, or overflow error. Note that an overflow error occurs at the input to the receive FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This register is not updated by subsequent errors until the buffer unloads and is reloaded, or the receive DMA is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ADD[12:0] r r r r r rr rr rr r r Bits [31:13] Bits [12:0] The offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error. Note that an overflow error occurs at the input to the receive FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This register is not updated by subsequent errors until the buffer unloads and is reloaded, or the receive DMA is reset. |
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