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AVRM2012 Datasheet(PDF) 8 Page - TDK Electronics

No. de pieza AVRM2012
Descripción Electrónicos  Chip varistors ESD/Voltage protection devices
PDF  12 Pages
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Fabricante Electrónico  TDK [TDK Electronics]
Página de inicio  http://www.tdk.com
Logo TDK - TDK Electronics

AVRM2012 Datasheet(HTML) 8 Page - TDK Electronics

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Please be sure to request delivery specifications that provide further details on the features and specifications of the products for proper and safe use.
Please note that the contents may change without any prior notice due to reasons such as upgrading.
Voltage Protection Devices
Chip varistors
Arrangements of components
(1) I was based on camber of substrate and suggested protocol of
chip varistors arrangement, as stress does not join to the utmost is
shown in following.
(2) In payment near by board, depending on mount position of chip
varistors, as mechanical stress varies, please refer to the following
diagram.
The order of A > B = C > D > E eases the stress.
Attention on a circuit board design
RoHS Directive Compliant Product
Compatible with lead-free solders
Substrate for flexural stress
Adverse events
Substrate for flexural stress
Good example
Direction of
surface solder
Solder the mountain fold as a
top.
Solder the mountain fold as a
bottom. [Please review the
italicized portion, as I am
unsure what you mean to con-
vey here.]
Chip
arrangements
(direction)
Mounted vertically to the per-
foration and slit.
Mounted horizontally to the
perforation and slit.
Distance from
perforation
and slit
portion
Close location is disadvanta-
geous of perforation and slit.
It is an advantage so distant
location away places the perfo-
ration and slit.
Perforation or slit
Perforation or slit
Perforation or slit
Perforation or slit
L1
(L1<L2)
L2
(L1<L2)
B
E
D
A
C
Slit
Perforation



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