SPEAR-07-NC03 datasheet(9/194 Pages) STMICROELECTRONICS

9 / 194 page

SPEAR-07-NC03

2 Features

9/194

Features

2.1

Architecture

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Integrated System For Ethernet Application

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48MHz, 3.3V I/O and 1.8V Internal Core Voltage

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ARM720T RISC Processor Core

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AMBA Rev. 2.0 System Bus Architecture

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IEEE802.3/Ethernet Compliant MAC Core

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USB Interface Solution (Host)

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IEEE1284 Interface Solution (Master)

2.2

ARM720T RISC Processor

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ARM7TDMI RISC Core

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8KB Unified Instruction/Data Cache

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Enlarged Write Buffer (8 words and 4 different addresses)

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Virtual Address Support with MMU

2.3

External Memory Interface

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16bit/8bit Memory Bus Support

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ROM/SRAM/Flash Static Memory Controller

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SDRAM/EDO DRAM Controller

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External I/O Bank Controller

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Independent Configurable Memory and I/O Banks

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Replaceable Memory and I/O Bank Addresses

2.4

IEEE802.3/Ethernet MAC

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10/100 MAC, MAC Host block, Station Management block, Address

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Compliant with IEEE 802.3 and 802.3u specifications

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Supports 10/100 Mb/s data transfer rates

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IEEE 802.3 Media Independent Interface (MII)

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Supports full and half duplex operations

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Check block and the Control Status Register (CSR) block

2.5

DMA Controller

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Dedicated Channels for MAC core, USB Host and IEEE1284 interface

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2 Channels general purpose DMA (Memory To Memory)

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