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BT815Q-R Datasheet(PDF) 52 Page - Bridgetek Pte Ltd. |
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BT815Q-R Datasheet(HTML) 52 Page - Bridgetek Pte Ltd. |
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52 / 64 page  Copyright © Bridgetek Pte Ltd 52 BT81X (815/6) Advanced Embedded Video Engine Datasheet Version 1.0 Document No.: BRT_000220 Clearance No.: BRT#126 6.4.2 SPI Interface Timing Figure 6-1 SPI Interface Timing Parameter Description VCCIO=1.8V VCCIO=2.5V VCCIO=3.3V Units Min Max Min Max Min Max Tsclk SPI clock period (SINGLE/DUAL mode) 33.3 33.3 33.3 ns Tsclk SPI clock period (QUAD mode) 33.3 33.3 33.3 ns Tsclkl SPI clock low duration 13 13 13 ns Tsclkh SPI clock high duration 13 13 13 ns Tsac SPI access time 4 3.5 3 ns Tisu Input Setup 4 3.5 3 ns Tih Input Hold 0 0 0 ns Tzo Output enable delay 16 13 11 ns Toz Output disable delay 13 11 10 ns Tod Output data delay 15 12 11 ns Tcsnh CSN hold time 0 0 0 ns Table 6-9 SPI Interface Timing Specifications |
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