Philips Semiconductors

Product specification

74ALS175

Quad D flip-flop

2

1991 Feb 08

853–1024 01670

FEATURES

DESCRIPTION

The 74ALS175 is a quad, edge-triggered D-type flip-flops with

individual D inputs and both Q and Q outputs. The common buffered

clock (CP) and master reset (MR) inputs load and reset (clear) all

flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one

setup time before the Low-to-High clock transition is transferred to

the corresponding flip-flop’s Q output.

All Q outputs will be forced Low independent of clock or data inputs

by a Low voltage level on the MR input. The device is useful for

applications where both true and complement outputs are required,

and the clock and master reset are common to all storage elements.

TYPE

TYPICAL

TYPICAL

SUPPLY CURRENT

(TOTAL)

74ALS175

70MHz

7mA

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

9

8

SF00718

Q3

Q3

D3

D2

Q2

Q2

CP

MR

Q0

Q0

D0

D1

Q1

Q1

GND

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

DRAWING

NUMBER

16-pin plastic DIP

74ALS175N

SOT38-4

16-pin plastic SO

74ALS175D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74ALS (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 – D3

Data inputs

1.0/1.0

20

µA/0.1mA

CP

Clock Pulse input (active rising edge)

1.0/1.0

20

µA/0.1mA

MR

Master Reset input (active-Low)

1.0/1.0

20

µA/0.1mA

Q0 – Q3

True outputs

20/80

0.4mA/8mA

Q0 – Q3

Complementary outputs

20/80

0.4mA/8mA

NOTE:

One (1.0) ALS unit load is defined as: 20

µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

GND = Pin 8

SF00719

4

5

12 13

D0 D1 D2 D3

CP

MR

9

1

2

3

7

6

10

11 15

14

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3

IEC/IEEE SYMBOL

R

C1

1D

SF00720

1

9

4

5

12

13

2

3

7

6

10

11

15

14