Philips Semiconductors

Product specification

74F153

Dual 4-line to 1-line multiplexer

2

1996 Jan 05

853–0100 16187

FEATURES

DESCRIPTION

The 74F153 is a dual 4-input multiplexer that can select 2 bits of

data from up to four sources selected by common Select inputs (S0,

S1). The two 4-input multiplexer circuits have individual active-Low

Enables (Ea, Eb) which can be used to strobe the outputs

independently. Outputs (Ya, Yb) are forced Low when the

corresponding Enables (Ea, Eb) are High.

The 74F153 is the logic implementation of a 2-pole, 4-position

switch where the switch is determined by the logic levels supplied to

the common select inputs.

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F153

7.0ns

12mA

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

Ya

I2b

I1b

I0b

I3b

Eb

S0

Ea

S1

I0a

I3a

I2a

I1a

9

8

GND

Yb

SF00146

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG.

DWG. #

16-pin plastic DIP

N74F153N

SOT38-4

16-pin plastic SO

N74F153D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

I0a – I3a

Port A data inputs

1.0/1.0

20

µA/0.6mA

I0b – I3b

Port B data inputs

1.0/1.0

20

µA/0.6mA

S0, S1

Common Select inputs

1.0/1.0

20

µA/0.6mA

Ea

Port A Enable input (active Low)

1.0/1.0

20

µA/0.6mA

Eb

Port B Enable input (active Low)

1.0/1.0

20

µA/0.6mA

Ya, Yb

Port A, B data outputs

50/33

1.0

µA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

Ya

7

GND = Pin 8

14

2

1

15

S0

S1

Ea

Eb

I1a

I2a

43

SF00147

I3a

I0a

65

Yb

9

I1b

I2b

12

13

I3b

I0b

10

11

IEC/IEEE SYMBOL

SF00148

1

6

5

EN

0

1

14

0

2

1

7

G

0

3

MUX

4

3

2

3

15

10

11

9

12

13